Referring to FIGS. 2 and 3, conventional power-on reset circuits are accompanied by problems in that the level of the input signal of the NAND 4 becomes instable during the period in which the source voltage REG outputted from the voltage regulator 9 is rising after the source voltage VDD has risen, whereby the through current flows from the source voltage VDD to the ground potential GND.
That is, the normal source voltage REG is not supplied to the monitoring unit 2 and to the inverter 3b as part of the level shifter 3 during the rise-up period up of the source voltage REG after the source voltage VDD has risen. Accordingly, the reset signal RS2 outputted from the monitoring unit 2 and the output signal of the inverter 3b are both brought to “L”. As a result, the NMOSs 3a and 3c are respectively brought to an off state during this period, so that the level of the reset signal RS3 outputted from the level shifter 3 becomes unstable.
Since the source voltage VDD has risen in this state, the reset signal RS1 is brought to “H”, and the PMOS 4a is turned off and the NMOS 4c is turned on. On the other hand, there is a fear that when the reset signal RS3 becomes unstable, the PMOS 4b and NMOS 4d are turned on simultaneously. This would result in the through current flowing from the source voltage VDD to the ground potential GND via the PMOS 4b and NMOSs 4c and 4d. Accordingly, there was a fear that a failure in operation would be incurred due to aged deterioration with the flow of the through current at each power-on.